A variable delay circuit has a function of delaying an input signal by a certain time and outputting the delayed signal. Delay time can be set by data input from the outside. Such a variable delay circuit is employed for making timing adjustments in such as instruments and communication apparatus, and it can have a variety of structures depending on the variable width and variable resolution of delay time. For example, a variable delay circuit of a digital circuit system having minute variable resolution of several tens of ps (pico seconds) is described below.
FIG. 10 is a block diagram illustrating a prior art four-value digital variable delay circuit having minute resolution. As shown in FIG. 10, this variable delay circuit comprises a common gate 10 for separating input signals V.sub.IN, wirings 25, 26, 27 and 28 having lengths successively lengthened from the wiring 25 to the wiring 28, driving gates 21, 22, 23 and 24 having outputs that are respectively connected to the wirings 25, 26, 27 and 28, and a selector 29 for selecting the outputs of the driving gates 21, 22, 23 and 24. The gate delay times vary according to the lengths of the wirings 25, 26, 27 and 28 that are respectively connected to the outputs of the driving gates 21, 22, 23 and 24. Utilizing these various delay times, delay signals respectively having slight time differences are produced to select a desired signal out of the delay signals with a control signal V.sub.CONT of the selector 29, whereby a desired variable delay output is obtained. In the prior art variable delay circuit, by appropriately selecting the lengths of the wirings 25, 26, 27 and 28 that are respectively connected to the driving gates 21, 22, 23 and 24, delay time difference of several tens of ps to several ps is produced and, in theory, it is possible to obtain a variable delay circuit having delay resolution of several tens of ps to several ps.
However, the prior art variable delay circuit has the problems described below.
More specifically, since the prior art variable delay circuit selects one of the driving gate outputs with the selector, delay resolution desired for the whole delay circuit cannot be obtained due to the delay time differences between paths in the selector. For example, even when the lengths of the wirings 25, 26, 27 and 28 are designed so that the delay times of the outputs of the driving gates 21, 22, 23 and 24 successively increase by 25 ps, if there is delay time difference of about 50 ps between the paths in the selector, a variable delay of 25 ps for the whole delay circuit is not produced.
Further, the delay between the paths in the selector is mostly due to the differences in threshold voltage V.sub.th between transistors constituting the selector. Therefore, the delay time difference between the paths in each IC chip is different, whereby it is impossible to correct the differences by circuit design, so that the prior art variable delay circuit is poor in yield.